Infineon Technologies last week introduced the automotive industry’s first LPDDR flash memory to support the development of new E/E (electrical and electronic) systems for semi-autonomous vehicles. Secure, reliable and real-time code execution, which is essential for automotive zone and domain control, is provided by the Infineon SEMPER X1 LPDDR flash solution.

Infineon Semper X1 LPDDR Flash

According to Infineon, the device enables 20 times faster random read transactions for real-time applications and up to eight times better performance than traditional NOR flash memory. It is no exaggeration to describe this type of performance improvement as remarkable.

Typical NOR flash memory is often called non-volatile storage, meaning that storage devices with that type of flash memory retain data without a battery or other powered voltage supply. This capability has made it possible for software-dependent cars to offer state-of-the-art features with improved safety and architectural flexibility.

Next-Gen Cars Are Computers on Wheels

As I’ve noted in previous columns, modern cars have evolved over the past 20 years into computers on wheels. The next generation of cars depend on state-of-the-art multicore computers built using modern manufacturing techniques.

Because autonomous driving scenarios require intelligence and real-time connectivity to meet the safety and dependability requirement, high-density integrated non-volatile memories are no longer a financially viable option. However, these sophisticated automotive real-time computers require more exceptional performance than current memory solutions offer.

Infineon built the SEMPER X1 with a proven LPDDR4 interface running at 3.2 GB/s and a multi-bank architecture to meet the performance and density needs of domain and zone controllers.

Infineon LPDDR Flash - for Automotive: Diagram

Traditional Safety-Critical Functions in Next-Gen Cars (Source: Infineon Technologies)

The resulting value proposition is quite compelling. Infineon duets flash memory with a LPDDR (Low Power Double Data Rate) interface to allow for more dramatic performance and scalability than xSPI NOR flash to meet the new requirements of automotive zone design. Infineon’s choice to use this interface is smart, given that the interface has been on the market for years and has a low-risk implementation reputation.

From a vehicle perspective, the transition to software-defined vehicle architecture has caused a memory challenge for next-generation auto designs. Traditional xSPI NOR flash memory is insufficient for a number of reasons, cost being the primary one. SEMPER XI leverages the LPDDR interface method from the DRAM industry to meet new computing requirements in the automobile industry.

Key Automotive Demands: Increasing Performance, Density Demands

The next generation of semi-autonomous automobiles require increasingly more flash memory and faster performance. For some time now cars have been moving towards zonal design without compromising real-time processing. These demands for higher performance cannot be met by what typical NOR flash storage provides today.

The growing number of domain and zone controllers appearing in next-generation semi-autonomous vehicles must process massive amounts of data in near real time while consolidating multiple safety-critical functions.

These zone controllers have intensive real-time computing requirements. While these controllers send information to the main ECU (Electronic Control Unit), these zonal controllers must also manage steering, engine, and other critical safety functions.

Automotive zone controllers are constantly being pushed to provide greater performance levels to meet these real-time processing requirements. A controller with integrated embedded memory on board cannot handle this increased level of complex processing.

Needs quick access to external flash

The processing requirements of next-generation automobile designs have driven a shift from real-time processors with a few CPU cores and onboard flash. At a high level, one could reasonably say that the development of semiconductor technology has led to a mismatch between CPUs and memory.

Given the cost pressures in the smart car and EV markets, adding onboard flash is not economically viable using today’s advanced semiconductor process nodes employed by those processor solutions.

The reality is that fast, real-time multicore processors that operate from external flash memory are necessary to meet the requirements of the next generation of automotive designs.

Automotive-qualified embedded flash technologies have difficulties with high cost (large die area) and lack of scalability on advanced manufacturing nodes. In addition, the industry required additional flash memory to accommodate the expanding code size and complexity.

xSPI is not scalable and runs out of gas

All of these factors influenced Infineon’s role in developing LPDDR flash memory.

Sandeep Krishnagowda, VP of Infineon Marketing and Applications, explained that the company has taken the initiative to help define the LPDDR memory range as the right solution to address the growing need for real-time compute capability for code execution by multicore processors. Used high-profile OEM feedback for. , This approach makes sense because fast random access is at the heart of LPDDR flash.

Undoubtedly, this method speeds up the execution rates. According to Infineon, when compared to a typical octal (x8) xSPI NOR flash chip, using LPDDR flash results in an astonishing 20x increase in performance. Conversely, toggling from real-time computations inside the CPU to those in external memory requires this performance improvement.

With its LPDDR interface, the SEMPER X1 flash can deliver throughput rates of up to 3.2 Gb/s. Its multi-bank design allows for over-the-air firmware changes without downtime, which is important in autonomous driving scenarios. The device also includes advanced error correction and other security measures, and is ISO 26262 ASIL-B compliant.

Other factors come into play in driving the replacement of XSPI with LPDDR flash.

First, xSPI, as a legacy interface, is not only very sluggish but does not scale well enough to meet future needs. This important factor is also propelling the demand for LPDDR Flash. In addition, the xSPI devices on the market today use a Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) approach that cannot exceed 200 MHz, requiring high-bandwidth solutions.

Given that context, traditional octal xSPI flash devices are unsuitable for code execution because they cannot accommodate today’s gigahertz multicore processors.

closing thoughts

Infineon’s SEMPER X1 is an essential step in that direction as it features more complex engine control and real-time decision making supported by a memory architecture that can evolve independently of the CPU.

This new non-volatile memory category will be fascinating to watch as the ecosystem grows. My recent podcast with Krishnagowda provided some interesting insight into the disruptive implications of this new announcement.

Infineon has been a bit coy about market categories beyond the auto space that LPDDR flash memory could appeal to.

Linus Wong, director of product management for Infineon’s SEMPER X1, acknowledges that storage, security and medical applications could see tremendous interest in this new storage capability. “When we look at these secondary markets, it really comes down to the enhanced value proposition [usage models] that can take advantage of latency improvements measured in thousandths of a second,” he said.

Finally, it is not unimportant that Infineon has taken an industry leadership role in releasing this new memory solution. Company pride, a long-standing reputation for design-in excellence, and a history of solid execution that is critical to high ASP next-gen autos are all tailwinds that favorably support market acceptance of LPDDR flash memory.

According to Infineon, the SEMPER X1 is now undergoing sampling, with a commercial release slated for sometime in 2024.